When a LSI (Large Scale Integrated Circuit) which operates in high-speed is designed using a fine processing technology, it is important to design a layout in consideration of noise which occurs in a wiring connecting power supply terminals (power supply line) of the LSI. In this case, it is effective to arrange a capacitor cell, which absorbs noise that occurs in a power supply line using the battery charging and discharging function that a capacitor have, in such a way that it is connected to the power supply line.
In LSI design, a capacitance value required to reduce noise which occurs in a power supply line is obtained using a power supply analysis tool based on a layout of a logic circuit. Then, a capacitor cell is inserted by a layout tool so that required capacitance may be filled. For example, in a layout design phase, a method to determine a capacitance value to be added to a semiconductor integrated circuit is disclosed in Japanese Patent Application Laid-Open No. 2002-288253 (patent document 1). In the method described in patent document 1, a power grid on a layout of an integrated circuit is divided into a plurality of areas, and a capacitance value which is required is determined for each area.
When a capacitor cell is arranged, in an area where density of arranged wiring is high, there is a case where an enough capacitor cell may not be able to be arranged because of interfering of a wiring in the capacitor cell and a wiring of a LSI already arranged. In such a case, there is a risk that backtracking such as layout change of the LSI is needed in order to reduce density of arranged wiring, and that a chip size is forced to increase for the purpose of such as securing an extra space around the area of arranged wiring.
For this reason, it is necessary to arrange a cell considering density of arranged wirings and wiring structure. In Japanese Patent Application Laid-Open No. 2006-49782 (patent document 2), a layout method which arranges an area pad cell and a wiring pattern cell based on wiring information and wiring structure is disclosed. As a result, a layout design that satisfies a design rule can be generated, while securing a connection between cells and a connection between a cell and other wiring patterns by a pin and a contact in a cell boundary area and an internal wiring area.
Meanwhile, a method in which interference with existing wirings is prevented by preparing a plurality of capacitor cells having different wiring patterns in advance and exchanging a capacitor cell according to a wiring situation of a LSI is conceivable (for example, refer to Japanese Patent Application Laid-Open No. 2005-276970 (patent document 3)).
However, in these related technologies, it is necessary to predict a wiring situation of a LSI to some extent, and, in some cases, to prepare many capacitor cells such as of the same size having a plurality of wiring patterns beforehand.
Moreover, it is disclosed in Japanese Patent Application Laid-Open No. 2000-138289 (patent document 4) that an internal wiring for unnecessary clock signals is eliminated to decrease parasitic capacitance. However, the technology described in this patent document 4 aims at speeding up and reduction in chip size of a LSI, and thus does not relate to noise reduction.